Semiconductor device having gate electrode of staked structure including polysilicon layer and metal layer and method of manufacturing the same

ABSTRACT

The present invention provides a semiconductor device, comprising a gate electrode of a stacked structure consisting of a polysilicon layer and a metal layer, a cap insulating film formed on the gate electrode, and a gate side wall film formed on the side wall of the gate electrode. The cap insulating film consists of an insulating film containing a silicon oxide-based layer and a silicon nitride layer and serves to protect the upper surface of the gate electrode. Further, the gate side wall film consists of an insulating film containing a silicon nitride film and a silicon oxide film and serves to protect the side surface of the gate electrode.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device including a MOSfield effect transistor having a gate electrode of a stacked structureincluding a polycrystalline silicon (polysilicon) layer and a metallayer and a method of manufacturing the same.

In recent years, a MOS field effect transistor (hereinafter referred toas MOS-FET) is being miniaturized, and the operating speed of theMOS-FET is being promoted. With increase in the operating speed, aproblem of signal delay, i.e., gate delay, is generated. The gate delaydepends on the product between the capacitance and the resistance of thegate wiring. In order to suppress the gate delay, used is a gateelectrode of a stacked structure consisting of a polysilicon layer and ametal layer, e.g., a stacked structure consisting of a polysilicon layerand a tungsten (W) layer.

FIG. 1 is a cross sectional view showing the construction of aconventional semiconductor device having a gate electrode of a stackedstructure consisting of a polysilicon layer and a tungsten layer. Asshown in the drawing, a gate insulating film 101 is formed on asemiconductor substrate 100, and a gate electrode of a stacked structureconsisting of a polysilicon layer 102 and a tungsten layer 103 is formedon the gate insulating film 101.

In manufacturing a semiconductor device provided with such a gateelectrode, the tungsten layer 103 tends to be oxidized under anoxidizing atmosphere or tends to be dissolved in a process solutionconsisting of sulfuric acid and hydrogen peroxide solution. To overcomethese difficulties, the gate electrode is covered with a cap film 104and a gate side wall film 105. Each of these cap film 104 and gate sidewall film 105 consists of a silicon nitride film. When it comes to themanufacturing process of the device shown in FIG. 1, a resist removingstep is performed after the etching step by lithography in preparationfor a wiring step with, for example, aluminum. In this resist removingstep, used is a mixed solution consisting of sulfuric acid and hydrogenperoxide solution.

It should also be noted that it is important to decrease the parasiticresistance in order to achieve further miniaturization of thesemiconductor device for increasing the degree of integration and toallow the semiconductor device to be operated at a high speed. In viewof these requirements, used is a salicide technology that is effectivefor decreasing the diffusion layer resistance and the contactresistance. In the salicide technology, a metal such as titanium orcobalt is deposited on a diffusion layer, followed by applying a heattreatment so as to bring about reaction between silicon in the diffusionlayer and the deposited metal, thereby forming a silicide layer in thediffusion layer.

The salicide technology includes a selective etching step forselectively removing the unreacted metal, with the silicide formed bythe heat treatment left unremoved. A mixed solution consisting ofsulfuric acid and hydrogen peroxide solution is used in this selectiveetching step.

As described above, the gate electrode of a stacked structure consistingof a polysilicon layer and a tungsten layer is treated in a subsequentstep with a chemical solution containing hydrogen peroxide solution.What should be noted is that tungsten is dissolved in the particularchemical solution, making it necessary to cover the tungsten layer withan insulating film.

Tungsten is poor in its resistance to oxidation. Therefore, it isdesirable for the insulating film to be formed of a material that can bedeposited under a reducing atmosphere and that is capable of inhibitingintrusion of an oxidizing agent in the subsequent heating step. Ingeneral, the insulating film is formed of silicon nitride.

However, defects such as pin holes tend to be formed by stress in thesilicon nitride film. Naturally, defects such as pin holes are formed inmany cases in the silicon nitride film covering the gate electrode,making it difficult to prevent a mixed solution consisting of sulfuricacid and hydrogen peroxide solution from permeating through the pinholes so as to dissolve tungsten in the selective etching step with themixed solution in the subsequent step of forming a silicide layer in thesource and drain regions (diffusion layers). It should also be notedthat the removing solution for removing the resist film used for thepatterning intrudes through the pin holes made in the silicon nitridefilm used as a gate protective film (cap film and gate side wall film)so as to dissolve tungsten and, thus,_to bring about breakage of thegate electrode.

Further, when a silicon nitride film acting as a cap film is depositedon the tungsten layer, tungsten is oxidized by the oxidizing-agentwithin the atmosphere so as to bring about a morphological deteriorationof the surface.

Still further, when a silicon nitride film is deposited to form a gateside wall film on the side surface of the gate electrode, an oxidizingagent within the atmosphere tends to intrude through the defects such aspin holes of the silicon nitride film so as to oxidize the tungstenlayer included in the gate electrode.

BRIEF SUMMARY OF THE INVENTION

An object of the present invention, which has been achieved in anattempt to overcome the above-noted problems inherent in the prior art,is to provide a semiconductor device, in which the gate electrode of astacked structure consisting of a polysilicon layer and a metal layer isprevented from being broken or deteriorated, and a method ofmanufacturing the particular semiconductor device.

According to a first aspect of the present invention, there is provideda semiconductor device, comprising a gate electrode having a stackedstructure of a polysilicon layer and a metal layer, and a side wallinsulating film formed on a side wall of the gate electrode forprotecting the side wall of the gate electrode, the side wall insulatingfilm having a silicon oxide layer and at least two layers of siliconnitride.

According to a second aspect of the present invention, there is provideda semiconductor device, comprising a gate electrode having a stackedstructure of a polysilicon layer and a metal layer, a cap insulatingfilm formed on a upper surface of the gate electrode for protecting theupper surface of the gate electrode, the cap insulating film having atleast two layers of silicon nitride, and a side wall insulating filmformed on a side wall of the gate electrode for protecting the side wallof the gate electrode, the side wall insulating film having a siliconoxide layer and at least two layers of silicon nitride.

According to a third aspect of the present invention, there is provideda method of manufacturing a semiconductor device, comprising the stepsof forming a gate electrode having a stacked structure of a polysiliconlayer and a metal layer on a gate insulating film formed on asemiconductor substrate, forming a side wall insulating film on a sidewall of the gate electrode, the side wall insulating film having asilicon oxide layer and at least two layers of silicon nitride.

According to a fourth aspect of the present invention, there is provideda method of manufacturing a semiconductor device, comprising the stepsof forming a gate electrode having a stacked structure of a polysiliconlayer and a metal layer on a gate insulating film formed on asemiconductor substrate, forming a first silicon nitride film on a uppersurface of the gate electrode, forming a second silicon nitride film ona side wall of the gate electrode, forming a third silicon nitride filmto cover the first and second silicon nitride films, and forming a firstsilicon oxide film on that portion of the third silicon nitride filmwhich is positioned on the side wall of the gate electrode.

According to a fifth aspect of the present invention, there is provideda method of manufacturing a semiconductor device, comprising the stepsof forming a stacked structure forming a gate electrode and having apolysilicon layer and a metal layer on a gate insulating film formed ona semiconductor substrate, forming an insulating film including a firstsilicon nitride film on the stacked structure, processing the stackedstructure and the insulating film to form a gate electrode, forming asecond silicon nitride film on the semiconductor substrate having thegate electrode formed thereon, anisotropically etching the secondsilicon nitride film to allow the second nitride film to remain on aside wall of the gate electrode, forming a third silicon nitride film onthe semiconductor substrate having the second silicon nitride filmpartly remaining thereon, forming a silicon oxide film on the thirdsilicon nitride layer, and anisotropically etching the silicon oxidefilm to allow the silicon oxide film to remain on the side wall of thegate electrode.

In the semiconductor device of the present invention, the gate electrodeis covered with a stacked structure having a silicon oxide layer and asilicon nitride layer. Since the silicon oxide layer prevents a chemicalsolution filling the defects such as pin holes of the silicon nitridefilm from being brought into contact with the gate electrode. As aresult, the metal layer such as a tungsten layer included in the gateelectrode is not dissolved in the chemical solution nor oxidized by thechemical solution.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently preferred embodiments ofthe invention, and together with the general description given above andthe detailed description of the preferred embodiments given below, serveto explain the principles of the invention.

FIG. 1 is a cross sectional view showing the construction of aconventional semiconductor device;

FIG. 2 is a cross sectional view showing the construction of asemiconductor device according to a first embodiment of the presentinvention;

FIG. 3 is a cross sectional view showing the construction of asemiconductor device according to a modification of the first embodimentof the present invention;

FIG. 4 is a cross sectional view showing a first step of a method ofmanufacturing a semiconductor device according to a first embodiment anda modification thereof of the present invention;

FIG. 5 is a cross sectional view showing a second step of a method ofmanufacturing a semiconductor device according to a first embodiment anda modification thereof of the present invention;

FIG. 6 is a cross sectional view showing a third step of a method ofmanufacturing a semiconductor device according to a first embodiment anda modification thereof of the present invention;

FIG. 7 is a cross sectional view showing a fourth step of a method ofmanufacturing a semiconductor device according to a first embodiment anda modification thereof of the present invention;

FIG. 8 is a cross sectional view showing a fifth step of a method ofmanufacturing a semiconductor device according to a first embodiment anda modification thereof of the present invention;

FIG. 9 is a cross sectional view showing a sixth step of a method ofmanufacturing a semiconductor device according to a first embodiment anda modification thereof of the present invention;

FIG. 10 is a cross sectional view showing a seventh step of a method ofmanufacturing a semiconductor device according to a first embodiment anda modification thereof of the present invention;

FIG. 11 is a cross sectional view showing an eighth step of a method ofmanufacturing a semiconductor device according to a first embodiment anda modification thereof of the present invention;

FIG. 12 is a cross sectional view showing a ninth step of a method ofmanufacturing a semiconductor device according to a first embodiment anda modification thereof of the present invention;

FIG. 13 is a cross sectional view showing a tenth step of a method ofmanufacturing a semiconductor device according to a first embodiment anda modification thereof of the present invention;

FIG. 14 is a cross sectional view showing an eleventh step of a methodof manufacturing a semiconductor device according to a first embodimentof the present invention;

FIG. 15 is a cross sectional view showing a first step of another methodof manufacturing a semiconductor device according to a first embodimentof the present invention;

FIG. 16 is a cross sectional view showing a second step of anothermethod of manufacturing a semiconductor device according to a firstembodiment of the present invention;

FIG. 17 is a cross sectional view showing a third step of another methodof manufacturing a semiconductor device according to a first embodimentof the present invention;

FIG. 18 is a cross sectional view showing a fourth step of anothermethod of manufacturing a semiconductor device according to a firstembodiment of the present invention;

FIG. 19 is a cross sectional view showing a fifth step of another methodof manufacturing a semiconductor device according to a first embodimentof the present invention;

FIG. 20 is a cross sectional view showing the construction of asemiconductor device according to a second embodiment of the presentinvention;

FIG. 21 is a cross sectional view showing a first step of a method ofmanufacturing a semiconductor device according to the second embodimentof the present invention;

FIG. 22 is a cross sectional view showing a second step of a method ofmanufacturing a semiconductor device according to the second embodimentof the present invention;

FIG. 23 is a cross sectional view showing a third step of a method ofmanufacturing a semiconductor device according to the second embodimentof the present invention;

FIG. 24 is a cross sectional view showing a fourth step of a method ofmanufacturing a semiconductor device according to the second embodimentof the present invention;

FIG. 25 is a cross sectional view showing a fifth step of a method ofmanufacturing a semiconductor device according to the second embodimentof the present invention;

FIG. 26 is a cross sectional view showing a semiconductor deviceaccording to a third embodiment of the present invention;

FIG. 27 is a cross sectional view showing a first step of a method ofmanufacturing a semiconductor device according to the third embodimentof the present invention;

FIG. 28 is a cross sectional view showing a second step of a method ofmanufacturing a semiconductor device according to the third embodimentof the present invention;

FIG. 29 is a cross sectional view showing a third step of a method ofmanufacturing a semiconductor device according to the third embodimentof the present invention;

FIG. 30 is a cross sectional view showing a fourth step of a method ofmanufacturing a semiconductor device according to the third embodimentof the present invention; and

FIG. 31 is a cross sectional view showing a fifth step of a method ofmanufacturing a semiconductor device according to the third embodimentof the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Some embodiments of the present invention will now be described withreference to the accompanying drawings.

The construction of a semiconductor device according to a firstembodiment of the present invention will be described first. The firstembodiment is directed to an n-channel type MOS transistor (hereinafterreferred to as nMOS transistor). However, this embodiment can also beapplied to a p-channel MOS transistor (hereinafter referred to as PMOStransistor).

FIG. 2 is a cross sectional view showing the construction of asemiconductor device according to the first embodiment of the presentinvention. As shown in the drawing, an element separating region 11 forseparating element regions is formed in a silicon semiconductorsubstrate 10, and a gate insulating film 12 consisting of silicon oxide(SiO₂) film is formed on the element region.

A gate electrode of a stacked structure consisting of a polysiliconlayer having a thickness of about 100 nm and a metal film, e.g.,tungsten film 14 having a thickness of about 100 nm is formed on thegate insulating film 12. A silicon nitride film 15 having a thickness ofabout 200 nm is formed on the gate electrode, and another siliconnitride film 16 having a thickness of about 80 nm is formed on thesilicon nitride film 15. These silicon nitride films 15 and 16collectively form a cap film acting as a gate protective film.

A silicon nitride film 17 having a thickness of about 10 nm is formed tocover side surfaces of the gate electrode and the cap film. Further, thesilicon nitride film having a thickness of about 80 nm covers the outersurface of the silicon nitride film 17, and a silicon oxide-based film,e.g., a silicon oxide film 18 (a BPSG(Boron-Phospho-Silicate Glass) filmor a PSG (Phospho-Silicate Glass) film) is formed to cover the siliconnitride film 16. These silicon nitride films 17, 16 and silicon oxidefilm (or BPSG film or PSG film) 18 collectively form a gate side wallfilm 19 acting as a gate protective film.

An n-extension 20 and a p-extension (not shown) acting as source anddrain regions are selectively formed within an nMOS and a PMOS formed inthe semiconductor substrate 10. These n-extension 20 and p-extension arepositioned on both edge portions of the gate electrode. Further, ann⁺-type diffusion layer 21 and a p⁺-type diffusion layer (not shown) areformed on the outside of the n-extension 20 and the p-extension,respectively. The semiconductor device according to the first embodimentof the present invention is constructed as described above.

FIG. 3 shows a modification of the first embodiment of the presentinvention. In this modification, a silicon oxide-based film 22 isinterposed between the silicon nitride film 15 acting as a cap film andthe silicon nitride film 16. Further, a silicon oxide-based film 22(hereinafter referred to as an oxide film) is interposed between thesilicon nitride film 17 acting as a gate side wall film and the siliconnitride film 16.

The semiconductor device of the first embodiment and the modificationthereof is manufactured as described in the following.

Specifically, FIGS. 4 to 14 collectively show how to manufacture thesemiconductor device of the first embodiment and the modificationthereof.

In the first step, the element separating region 11 is formed in thesilicon semiconductor substrate 10 by a burying oxidizing method,followed by performing ion implantation for forming a well, a channel,etc. Then, a thermal oxidation is applied to the semiconductor substrate10 under an oxidizing atmosphere of a high temperature so as to form thegate insulating film 12 consisting of silicon oxide on the semiconductorsubstrate 10.

In the next step, a polysilicon layer 13 having a thickness of 100 nmand constituting the lowermost layer of a gate electrode having astacked structure is formed by a CVD method on the gate insulating film12, as shown in FIG. 5. Then, the polysilicon layer 13 is doped with,for example, phosphorus (P) by an ion implantation method at a dose of5×10¹⁵ cm⁻² and under an accelerating energy of 10 keV, followed by anannealing treatment at 850° C. for 30 minutes so as to diffuse theimplanted phosphorus ions into the polysilicon layer 13. In this step,it is possible to selectively introduce, for example, phosphorus ionsinto the nMOS transistor-forming region and boron ions into the pMOStransistor-forming region using masks formed by lithography method.

Then, a metal layer, e.g., a tungsten layer 14, is deposited in athickness of 100 nm by a sputtering method on the polysilicon layer 13.Further, a silicon nitride film 15 acting as a cap film of the gateelectrode is deposited in a thickness of 200 nm by a CVD method to forma stacked structure consisting of the polysilicon layer 13, the tungstenlayer 14 and the silicon nitride layer 15. The stacked structure ispatterned by a lithography method to form a gate electrode, as shown inFIG. 6. After formation of the gate electrode, the polysilicon layer 13is selectively oxidized under an atmosphere containing water vapor andhydrogen.

Further, the silicon nitride film 17 is deposited by a CVD method in athickness of 10 nm to cover the side surfaces of the gate electrode, thesilicon nitride film 15 acting as a cap film, and the semiconductorsubstrate 10, as shown in FIG. 7. Then, the n-extension 20 and thep-extension (not shown), which form source and drain regions, are formedby selective ion implantation into the nMOS transistor-forming regionand the pMOS transistor-forming region, respectively, using masks formedby lithography method. In this embodiment, the n-extension 20 and thep-extension were formed after deposition of the silicon nitride film 17.Alternatively, it is possible to form first the n-extension 20 and thep-extension, followed by depositing the silicon nitride film 17.

In the next step, the silicon nitride film 17 is anisotropically etchedby a reactive ion etching (RIE) method without using a mask pattern of aresist film to permit the silicon nitride film 17 to be left unremovedon the side surfaces of the gate electrode, as shown in FIG. 8. In themethod of manufacturing a semiconductor device according to the firstembodiment of the present invention, the anisotropic etching isperformed under the conditions that a silicon oxide-based film is notformed on the side surfaces of the gate electrode and on the siliconnitride film 17 and the cap film (silicon nitride film) 15. On the otherhand, in the modification of the first embodiment, the anisotropicetching is performed under the conditions that the oxide film 22 (seeFIG. 3) is formed in a thickness of about 1 nm on the silicon nitridefilm 17 positioned on the side surface of the gate electrode and on thecap film 17.

Further, the silicon nitride film 16 is deposited by a CVD method in athickness of 80 nm on the silicon nitride film 17 positioned on the sidesurface of the gate electrode, the silicon nitride film 15 on the capfilm and on the semiconductor substrate 10, as shown in FIG. 9. Stillfurther, the silicon oxide film 18 (or the BPSG film or PSG film) isdeposited on the silicon nitride film 16.

Then, the silicon oxide film 18 is anisotropically etched as shown FIG.2. As a result, formed is the gate side wall film 19 consisting of thesilicon nitride films 17, 16 and the silicon oxide film 18. Further, then⁺-type diffusion layer 21 and the p⁺-type diffusion layer (not shown)forming source and drain regions are selectively formed in the nMOStransistor-forming region and the PMOS transistor forming region,respectively, by ion implantation, using masks prepared by lithographymethod. As a result, prepared is the gate electrode portioncharacterizing the first embodiment of the present invention.

On the other hand, in the modification of the first embodiment, theoxide film 22 having a thickness of about 1 nm is formed to cover thegate electrode, followed by depositing the silicon nitride film 16 in athickness of about 80 nm on the oxide film 22 and subsequentlydepositing the silicon oxide film (or BPSG film or PSG film) 18 on thesilicon nitride film 16 as in the first embodiment of the presentinvention.

Then, as shown in FIG. 3, the silicon oxide film 18 is anisotropicallyetched to form the gate side wall film 23 consisting of the siliconnitride film 17, the oxide film 22, the silicon nitride film 16 and thesilicon oxide film 18. Further, the n⁺-type diffusion layer 21 and thep⁺-type diffusion layer (not shown) forming source and drain regions areselectively formed in the nMOS transistor-forming region and the pMOStransistor forming region, respectively, by ion implantation, usingmasks prepared by lithography method.

In the subsequent steps, the ordinary manufacturing process of MOS-FETis employed for manufacturing the semiconductor devices of the firstembodiment and the modification thereof.

For example, the subsequent manufacturing process in the firstembodiment of the present invention is as follows. In the first step, aresist pattern 24 is selectively formed on the gate electrode alone, asshown in FIG. 10, followed by etching the silicon nitride film 16positioned on the gate insulating film 12 except the region around thegate electrode, as shown in FIG. 11. Further, the resist pattern 12 isremoved, as shown in FIG. 12.

In the next step, the gate insulating film 12 positioned on the n⁺-typediffusion layer 21 is removed by treatment with a dilute hydrofluoricacid, followed by depositing a titanium layer in a thickness of 20 nmand, then a titanium nitride layer in a thickness of 70 nm andsubsequently applying a lamp annealing at 650° C. for 30 seconds under anitrogen gas atmosphere. As a result, reaction is carried out betweenthe n⁺-type diffusion layer 21 and titanium to form a titanium silicidefilm. Then, the unreacted titanium and titanium nitride are selectivelyremoved by the treatment with a mixed solution consisting of sulfuricacid and hydrogen peroxide solution. Further, a change in the phase ofthe titanium silicide layer is brought about by a lamp annealing at 800°C. for 30 seconds so as to form a C54 phase 25 having a low resistivity,as shown FIG. 13.

After formation of the C54 phase layer 25, an interlayer insulating filmsuch as a BPSG film is deposited in a thickness of 700 nm, followed byforming a contact hole in the interlayer insulating film. Further, aconductive film is deposited on the resultant structure, Followed bypatterning the conductive film to form a wiring layer.

FIG. 14 is a cross sectional view showing a semiconductor deviceprepared by forming the contact hole noted above by self-alignment,followed by forming the wiring layer noted above. It should be notedthat and an extension and a silicide film are not formed in thesemiconductor device shown in FIG. 14. The BPSG film 26 covering the twogate electrodes is removed in forming the contact hole so as to exposethe n⁺-type diffusion layer 21 to the outside. Then, a conductive filmsuch as a metal film is deposited on the resultant structure includingthe inner space of the contact hole. Further, the conductive film ispatterned to form a wiring 27 connected to the n⁺-type diffusion layer21.

The semiconductor device of the first embodiment can be manufactured byanother method. Specifically, FIGS. 15 to 19 collectively show anothermethod of manufacturing the semiconductor device according to the firstembodiment of the present invention.

A structure similar to that shown in FIG. 8 is obtained in the firststep. Specifically, a stacked structure formed on the gate insulatingfilm 12 on the silicon semiconductor substrate 10 and consisting of thepolysilicon layer 13, the tungsten layer 14 and the silicon nitridelayer 15 is processed to form the gate electrode, followed by formingthe n-extension 20 for the source and drain regions and subsequentlyforming the thin silicon nitride film 17 having a thickness of about 20nm. Then, the silicon nitride film 17 is anisotropically etched to formthe silicon nitride film covering the side surface of the gateelectrode, thereby obtaining a structure similar to that shown in FIG.8. Further, the silicon nitride film 16 having a thickness of 150 nm isformed to cover the n-extension 20 and the gate electrode, as shown inFIG. 15.

In the next step, the resultant structure is coated with the resist 28,followed by etch back such that more than half the gate electrodeprojects from the resist 28 and the n-extensions 20 in the source anddrain regions are covered with the resist 28, as shown in FIG. 16.

Then, a silicon oxide film 29 is deposited by a liquid phase selectivecrystal growth on that portion of the gate electrode which is notcovered with the resist 28, as shown in FIG. 17. Also, the resist 28 isremoved by an asher to selectively expose the silicon nitride film 16 tothe outside, followed by isotropically etching the exposed portion ofthe silicon nitride film 16 with CDE or hot phosphoric acid. As aresult, the silicon nitride film 15 forming the cap film and the siliconnitride film 17 forming a gate side wall film are covered with aseamless silicon nitride film 16. Incidentally, an anisotropic etchingcan also be employed in place of the isotropic etching employed foretching the silicon nitride film 16.

In the next step, the silicon oxide film (or BPSG film or PSG film) 18is deposited in a thickness of 60 nm on the resultant structure by a CVDmethod, followed by etching back the silicon oxide film 18 by ananisotropic etching to form the gate side wall film, as shown in FIG.19.

Further, arsenic (As) is introduced into the nMOS transistor region bymeans of ion implantation under an accelerating energy of 45 keV and ata dose of 5×10¹⁵ cm⁻². Also, BF₂ ⁺ is introduced into the pMOStransistor region by means of ion implantation under an acceleratingenergy of 35 keV and at a dose of 3.5×10¹⁵ cm⁻². Further, a heattreatment is applied at 950° C. for 10 seconds to form n⁺-type diffusionlayers 21 forming the source and drain regions, as shown in FIG. 19.Still further, a silicide film is formed on the n⁺-type diffusion layers21 by using a salicide technology, followed by depositing an interlayerinsulating film such as the BPSG film 26 and subsequently forming thewiring layer 27, as in the method shown in FIGS. 13 and 14.

In the manufacturing method described above, one lithography step can beomitted, compared with the manufacturing method shown in FIGS. 4 to 14.

In the first embodiment described above, the tungsten layer 14 includedin the gate electrode is covered with the silicon oxide film 18constituting the gate side wall film. Therefore, even if defects such aspin holes are present in the silicon nitride films 16 and 17constituting the other gate side wall films, the mixed solution ofsulfuric acid and hydrogen peroxide solution used in the step of, forexample, selectively removing the unreacted titanium and titaniumnitride is prevented by the silicon oxide film 18 from intruding intothe gate electrode. Naturally, the tungsten layer 14 is not dissolved inthe mixed solution noted above.

In the modification of the first embodiment described above, thetungsten layer 14 included in the gate electrode is covered with thesilicon oxide films 18 and 22 forming the gate side wall films.Therefore, even if defects such as pin holes are present in the siliconnitride films 16 and 17 constituting the other gate side wall films, themixed solution of sulfuric acid and hydrogen peroxide solution used inthe step of, for example, selectively removing the unreacted titaniumand titanium nitride is prevented by the silicon oxide films 18 and 22from intruding into the gate electrode. Naturally, the tungsten layer 14is not dissolved in the mixed solution noted above. Further, thetungsten layer 14 is covered with the silicon oxide film 22 used as acap film. Therefore, even if defects such as pin holes are present inthe silicon nitride films 15 and 16, the mixed solution consisting ofsulfuric acid and hydrogen peroxide solution is prevented by the siliconoxide film 22 from intruding into the gate electrode. Naturally, thetungsten layer 14 is not dissolved in the particular mixed solution.

It should also be noted that, in the step of forming a contact hole byself-alignment, the silicon nitride film 16 acting as a gate protectivefilm (cap film) is formed on the gate electrode. Since the siliconnitride film 16 acts as an etching stopper on the gate electrode, thegate electrode is prevented from being corroded.

The silicon nitride film 15 can be formed by a single depositingoperation. Alternatively, it is possible to repeat several times thesilicon nitride deposition and interruption of the deposition such thatthe nitride film 15 is formed by several times of the silicon nitridedeposition. In this case, even if pin holes are formed in the siliconnitride layer deposited in the previous depositing operation, these pinholes are closed by the silicon nitride layer deposited in thesubsequent depositing operation. It follows that it is possible toprevent the pin holes from extending throughout the silicon nitride film15 in its thickness direction. It is also possible to form each of thesilicon nitride films 16 and 17 by several times of the silicon nitridedeposition. In this case, the mixed solution consisting of sulfuric acidand a hydrogen peroxide solution is prevented from permeating throughthe silicon nitride film 15, 16 or 17 to reach the gate electrode.

As described above, according to the first embodiment of the presentinvention, a mixed solution consisting of sulfuric acid and hydrogenperoxide solution is prevented from intruding through defects such aspin holes present in the silicon nitride film acting as a gateprotective film (cap film and gate side wall film) into the tungstenlayer included in the gate electrode in the selective etching step withthe particular mixed solution for forming silicide layers in the sourceand drain regions (salicide technology). As a result, the tungsten layerincluded in the gate electrode is prevented from being dissolved in theparticular mixed solution. Also, the removing solution for removing theresist used in the patterning step is prevented from intruding throughdefects such as pin holes of the silicon nitride film forming the gateprotective film (cap film and gate side wall film) into the tungstenlayer included in the gate electrode in the resist removing step.Naturally, the tungsten layer included in the gate electrode isprevented from being dissolved in the removing solution.

Incidentally, in the first embodiment and the modification thereofdescribed above, the gate electrode is of a stacked structure consistingof a polysilicon layer and a tungsten layer. However, the gate electrodeis not limited to the particular stacked structure. For example, it ispossible for the stacked structure to consist of a polysilicon layer andanother metal layer.

The semiconductor devices of the second and third embodiments of thepresent invention will now be described. The second and thirdembodiments produce additional prominent effects besides the effectsproduced by the first embodiment.

The construction of the semiconductor device according to the secondembodiment of the present invention will be described first. In thefollowing description, the technical idea according to the secondembodiment of the present invention is applied to an n-channel MOStransistor (nMOS transistor). However, the particular technical idea canalso be applied to a CMOS transistor including an p-channel MOStransistor (pMOS transistor).

FIG. 20 is a cross sectional view showing the construction of asemiconductor device according to the second embodiment of the presentinvention. As shown in the drawing, an element separation region 31 isformed on a semiconductor substrate 30, and a gate insulating film 32consisting of a silicon oxide (SiO₂) film is formed on the elementregion.

A gate electrode of a stacked structure consisting of a polysiliconlayer 33 and a metal film, e.g., a tungsten film 14, is formed on thegate insulating film 32 on the element region. Further, a cap film of astacked structure acting as a gate protective film is formed on the gateelectrode. The cap film consists of a silicon oxide film 35 having athickness of about 10 to 50 nm, a silicon nitride film 36 formed on thesilicon oxide film 35, and a silicon oxide film 37 having a thickness ofabout 10 to 20 nm and formed on the silicon nitride layer 36.

The silicon oxide film 37 having a thickness of about 10 to 20 nmextends to cover the side surfaces of the gate electrode and the capfilm. Further, a silicon nitride film 38 is formed to cover the sidesurfaces of the silicon oxide film 37. These silicon oxide film 37 andthe silicon nitride film 38 collectively form a gate side wall film 39acting as a gate protective film.

An n-extension 40 and a p-extension (not shown) for the source and drainregions are selectively formed in the nMOS transistor and the pMOStransistor within the semiconductor substrate 30 on both edge portionsof the gate electrode. Further, an n⁺-type diffusion layer 41 and ap⁺-type diffusion layer (not shown) are formed on the outside of then-extension 40 and the p-extension so as to form a semiconductor deviceof the second embodiment.

The semiconductor device of the second embodiment is manufactured asfollows. Specifically, FIGS. 20 to 25 are cross sectional viewscollectively the method of manufacturing the semiconductor device of thesecond embodiment.

As shown in FIG. 21, the element separation region 31 is formed withinthe silicon semiconductor substrate 30 by a burying oxidizing method,followed by applying an ion implantation for forming a well, a channel,etc. Then, a thermal oxidation is applied to the semiconductor substrate30 under an oxidizing atmosphere of a high temperature so as to form thegate insulating film 32 consisting of silicon oxide on the semiconductorsubstrate 30.

After formation of the gate insulating film 32, a polysilicon layer 33constituting the lowermost layer of the gate electrode of a stackedstructure is formed by a CVD method on the gate insulating film 32, asshown in FIG. 22. Then, phosphorus ions are introduced into thepolysilicon layer 33 by ion implantation at a dose of 5×10¹⁵ cm⁻² andunder an accelerating energy of 10 keV, followed by an annealingtreatment under a nitrogen gas atmosphere at 850° C. for 30 minutes soas to diffuse the implanted phosphorus ions into the polysilicon layer33. In this step, it is possible to selectively introduce, for example,phosphorus sons and boron ions by means of ion implantation into thenMOS transistor-forming region and the PMOS transistor-forming region,respectively, using a mask prepared by a lithography method.

In the next step, a metal layer, e.g., tungsten layer 34, is depositedin a thickness of 100 nm on the polysilicon layer 33, followed bydepositing a silicon oxide layer 35 acting as a cap film on the tungstenlayer 34 by a high frequency (RF) sputtering method under anon-oxidizing atmosphere of a low temperature. It should be noted thatthe surface of the tungsten layer 34 is physically covered with andpushed by the silicon oxide film 35. As a result, roughening of asurface morphology that accompanies the oxidation of the tungsten layer34 does not take place during deposition of a silicon nitride film 36 onthe silicon oxide film 35 in the subsequent step. Also, the RFsputtering treatment for depositing the silicon oxide film 35 isperformed under a high vacuum within the process chamber, with theresult that the tungsten layer 34 is not oxidized.

Further, the silicon nitride layer 36 acting as a cap film is depositedby a CVD method on the silicon oxide layer 35. Then, the stackedstructure including the layers 33, 34, 35 and 36 is patterned to form agate electrode, as shown FIG. 23.

In the next step, a silicon oxide film 37 is deposited by an RFsputtering method under a non-oxidizing atmosphere of a low temperatureto cover the silicon nitride layer 36 included in the gate protectivefilm, the side surfaces of the gate electrode and the surface of thesemiconductor substrate 10, as shown in FIG. 24. The silicon oxide film37 thus deposited serves to conceal defects such as pin holes present inthe silicon nitride film 36 so as to prevent an oxidizing agent fromintruding into a silicon nitride film 38 that is to be deposited in thesubsequent step. Also, since the silicon oxide film 37 is depositedunder a high vacuum, the tungsten layer 34 is not oxidized in spite ofthe presence of pin holes in the silicon nitride film 36.

Then, the n-extension 40 and the p-extension (not shown) of the sourceand drain regions are selectively formed by ion implantation in the nMOSand pMOS transistors, respectively, using a mask prepared by alithography method. Further, by the known selective after-oxidationtechnology, the silicon oxide film 37 alone is selectively oxidizedunder an atmosphere containing water vapor and hydrogen withoutoxidizing a metal layer such as the tungsten layer 34. By thisoxidation, the electric field applied to the gate insulating film at theedge of the gate electrode during operation of the transistor isprevented from being concentrated. At the same time, the density of thesilicon oxide film 37 deposited by the RF sputtering method is furtherincreased. Further, the silicon nitride film 38 is deposited in athickness of 80 nm by a CVD method on the silicon oxide film 37, asshown in FIG. 25.

In the next step, the silicon nitride film 38 is anisotropically etchedby a reactive ion etching (RIE) method without using a mask pattern of aresist film to leave the silicon nitride film 38 unremoved on the sidesurface of the gate electrode, as shown in FIG. 20, thereby forming thegate side wall film 39 consisting of the silicon oxide film 37 and thesilicon nitride film 38. Further, the n⁺-type diffusion layer 41 and thep⁺-type diffusion layer (not shown) constituting the source and drainregions are formed in the nMOS and pMOS transistor regions,respectively, by means of ion implantation, using a mask prepared by alithography method.

The gate electrode portion characterizing the semiconductor device ofthe second embodiment is prepared by the processes described above.Then, the ordinary process of manufacturing a MOS-FET is followed formanufacturing the semiconductor device according to the secondembodiment of the present invention.

For example, the subsequent manufacturing process in the secondembodiment of the present invention is as follows. In the first step, aresist pattern is selectively formed on the gate electrode alone as inthe first embodiment, followed by etching the silicon oxide film 37 andthe gate insulating film 32 positioned in the vicinity of the gateelectrode and subsequently removing the resist pattern. Then, a titaniumfilm is deposited in a thickness of 20 nm, followed by depositing atitanium nitride film in a thickness of 70 nm on the titanium film.Further, a lamp annealing is applied to the stacked structure consistingof the titanium film and the titanium nitride film at 650° C. for 30seconds under a nitrogen gas atmosphere so as to carry out reactionbetween the silicon semiconductor substrate 30 and titanium to form atitanium silicide film. Then, the unreacted titanium and titaniumnitride are selectively removed by using a mixed solution consisting ofsulfuric acid and hydrogen peroxide solution. Further, a phase change isbrought about in the titanium silicide film by a lamp annealing at 800°C. for 30 seconds so as to form a C54 phase of a low resistivity.

After formation of the C54 phase, an interlayer insulating film such asa BPSG film is deposited in a thickness of 700 nm, followed by forming acontact hole in the interlayer insulating film. Further, a conductivefilm is deposited on the resultant structure, followed by patterning theconductive film to form a wiring layer.

In the second embodiment, the tungsten layer 34 included in the gateelectrode is covered with the silicon oxide films 35, 37 acting as a capfilm and with the silicon oxide film 37 forming a gate side wall film.Therefore, even if defects such as pin holes are present in the siliconnitride films 36, 38 forming the cap film and the gate side wall film, amixed solution of sulfuric acid and hydrogen peroxide solution does notintrude into the gate electrode in the step of selectively removing theunreacted titanium and titanium nitride. Naturally, the tungsten layer34 included in the gate electrode is prevented from being dissolved inthe mixed solution.

It should also be noted that the upper surface of the tungsten layer 34is covered with the silicon oxide film 36 acting as a cap film. Thus,when the silicon nitride film 36 forming a cap film is deposited on thetungsten layer 34, the tungsten layer 34 is prevented from beingoxidized by the oxidizing agent within the atmosphere. Naturally, thesurface region of the tungsten layer 34 is prevented from themorphological deterioration.

Further, the side surface of the tungsten layer 34 included in the gateelectrode is covered with the silicon oxide film 37, and the uppersurface of the tungsten layer 34 is covered with the silicon oxide films35 and 37. Therefore, when the silicon nitride film 38 forming a gateside wall film is deposited on the side surface of the gate electrode,the oxidizing agent within the atmosphere is prevented from intrudinginto the gate electrode through the defects such as pin holes of thesilicon nitride film 36 used as a cap film. It follows that the tungstenlayer 34 included in the gate electrode is prevented from beingoxidized.

What should also be noted is that, in the step of forming a contact holeby self-alignment, the silicon nitride film 36 acting as a gateprotective film (cap film) is formed on the gate electrode. Since thesilicon nitride film 36 acts as an etching stopper on the gateelectrode, the gate electrode is not corroded.

The silicon nitride film 36 can be formed by a single depositingoperation. Alternatively, it is possible to repeat several times thesilicon nitride deposition and interruption of the deposition such thatthe nitride film 36 is formed by several times of the silicon nitridedeposition. In this case, even if pin holes are formed in the siliconnitride layer deposited in the previous depositing operation, these pinholes are closed by the silicon nitride layer deposited in thesubsequent depositing operation. It follows that it is possible toprevent the pin holes from extending throughout the silicon nitride film36 in its thickness direction. It is also possible to form the siliconnitride films 38 by several times of the silicon nitride deposition. Inthis case, the mixed solution consisting of sulfuric acid and a hydrogenperoxide solution is prevented from permeating through the siliconnitride film 36 or 38 to reach the gate electrode.

As described above, according to the second embodiment of the presentinvention, the mixed solution of sulfuric acid and hydrogen peroxidesolution used in forming the silicide layer in the source and drainregions (salicide technology) is prevented from intruding into the gateelectrode through the defects such as pin holes of the silicon nitridefilm used as a gate protective film (cap film and gate side wall film).As a result, it is possible to prevent the tungsten layer included inthe gate electrode from being dissolved in the mixed solution.Similarly, in the resist removing step for removing the resist used inthe patterning step, the removing solution for removing the resist isprevented from intruding into the gate electrode through the defectssuch as pin holes of the silicon nitride film used as a gate protectivefilm (cap film and gate side wall film). It follows that the tungstenlayer included in the gate electrode is prevented from being dissolvedin the removing solution.

Also, the upper surface of the tungsten layer included in the gateelectrode is covered with a silicon oxide film. Therefore, when asilicon nitride film used as a cap film is deposited on the tungstenlayer, the tungsten layer is prevented from being oxidized by theoxidizing agent present in the atmosphere and, thus, the surface of thetungsten layer is prevented from the morphological deterioration.

Further, the side surface and the upper surface of the tungsten layerincluded in the gate electrode are covered with a silicon oxide film.Thus, in the step of forming a silicon nitride film used as a gate sidewall film on the side surface of the gate electrode, the oxidizing agentwithin the atmosphere is prevented from intruding into the gateelectrode through the defects such as pin holes of the silicon nitridefilm used as a cap film. Naturally, the tungsten layer included in thegate electrode is prevented from being oxidized.

In addition, in the second embodiment of the present invention, asilicon oxide film having a low dielectric constant is formed betweenthe gate electrode and the silicon nitride film so as to suppress theparasitic capacitance, particularly, an overlap capacitance. Also, sincethe n⁺-type diffusion layer forming an active region is covered with asilicon oxide film, the active region is prevented from being exposeddirectly to a plasma in the step of forming a gate side wall by applyinga reactive ion etching to the silicon nitride fill. As a result, it ispossible to prevent impurities derived from the reactive ion etchingfrom entering the active region. It is also possible to suppress damagedone to the active region.

Incidentally, the second embodiment is directed to a gate electrode of astacked structure consisting of a polysilicon layer and a tungstenlayer. However, it is possible for the stacked structure to consist of apolysilicon layer and another metal layer.

In the second embodiment described above, the silicon oxide film isdeposited by a high frequency (RF) sputtering method. However, thesilicon oxide film can also be deposited by employing a low temperaturemethod that does not bring about oxidation such as a CVD method underatmospheric pressure or a magnetron sputtering method. Further, adeposition method carried out under vacuum such as a plasma-induced CVDmethod can also be used for depositing the silicon oxide film.

The construction of a semiconductor device according to a thirdembodiment of the present invention will now be described. The followingdescription is directed to an nMOS transistor. However, the technicalidea of the third embodiment can also be applied to a CMOS transistorincluding a pMOS transistor.

FIG. 26 is a cross sectional view showing the construction of asemiconductor device according to the third embodiment of the presentinvention. As shown in the drawing, an element separation region 51 forseparating element regions is formed in a semiconductor substrate 50.Also, a gate insulating film 52 consisting of silicon oxide (SiO₂) isformed on the semiconductor substrate 50.

A gate electrode consisting of a polysilicon layer 53 having a thicknessof about 100 nm and a metal layer, e.g., a tungsten layer 54 having athickness of about 100 nm is formed on the gate insulating film 52.Further, a stacked structure acting as a cap film used as a gateprotective film and consisting of a silicon nitride film 55 having athickness of about 50 nm, a silicon oxide film 56 having a thickness ofabout 10 nm, a silicon nitride film 57 having a thickness of about 100nm, and a silicon oxide film 58 having a thickness of about 10 nm isformed on the gate electrode.

Further, a silicon nitride 59 is formed to cover the side surfaces ofthe gate electrode, the silicon nitride film 55, the silicon oxide film56 and the silicon nitride film 57. Still further, a silicon oxide film58 and a silicon nitride film 60 are formed to cover the outer surfaceof the silicon nitride film 59. These silicon nitride film 59, siliconoxide film 58 and silicon nitride film 60 collectively constitute a gateside wall film 61.

An n-extension 62 and a p-extension (not shown) for the source and drainregions are selectively formed in the nMOS transistor and the pMOStransistor within the semiconductor substrate 50 on both edge portionsof the gate electrode. Further, an n⁺-type diffusion layer 63 and ap⁺-type diffusion layer (not shown) are formed on the outside of then-extension 62 and the p-extension so as to form a semiconductor deviceof the third embodiment.

The semiconductor device of the third embodiment is manufactured asfollows. Specifically, FIGS. 26 to 31 are cross sectional viewscollectively the method of manufacturing the semiconductor device of thethird embodiment.

As shown in FIG. 27, an element separation region 51 is formed by aburying oxidation method within a silicon semiconductor substrate 50,followed by applying an ion implantation to form a well region and achannel region. Then, a thermal oxidation is applied to thesemiconductor substrate 50 under an oxidizing atmosphere of a hightemperature so as to form the gate insulating film 52 consisting ofsilicon oxide.

In the next step, the polysilicon layer 53 forming the lowermost layerof the gate electrode is deposited in a thickness of 100 nm on the gateinsulating film 52 by a CVD method, as shown in FIG. 28. Then, thepolysilicon layer 33 is doped with phosphorus at a dose of 5×10¹⁵ cm⁻²by means of ion implantation performed under an accelerating energy of10 keV, followed by annealing at 850° C. for 30 minutes under a nitrogengas atmosphere so as to diffuse the implanted phosphorus into thepolysilicon layer 53. In this step, it is possible to introduceselectively phosphorus and boron into an nMOS transistor-forming regionand a pMOS transistor-forming region, respectively, by means of ionimplantation using a mask prepared by lithography method.

In the next step, a metal layer, e.g., a tungsten layer 54 is depositedin a thickness of 100 nm on the polysilicon layer 53 by a sputteringmethod. Further, the silicon nitride film 55 having a thickness of 50nm, the silicon oxide film 55 having a thickness of 10 nm, and thesilicon nitride film 57 having a thickness of 100 nm, which collectivelyform a cap film, are successively deposited by a CVD method on thetungsten layer 54. Further, the stacked structure constituting the capfilm and the stacked structure constituting the gate electrode arepatterned by a lithography method to form the gate electrode coveredwith the cap film, as shown in FIG. 29.

Further, the silicon nitride film 59 is deposited by a CVD method in athickness of 10 nm, as shown in FIG. 30, followed by anisotropicallyetching the silicon nitride film 59 by a reactive ion etching (RIE)method to allow the silicon nitride film 59 to remain on the side wallof the gate electrode, as shown in FIG. 31. Further, an n-extension 62and a p-extension (not shown) for the source and drain regions areselectively formed by ion implantation in the nMOS transistor and thePMOS transistor.

In the next step, the silicon oxide film 58 is deposited by a CVD methodin a thickness of 10 nm, followed by depositing the silicon nitride film60 in a thickness of 80 nm. Further, the silicon nitride film 60 isanisotropically etched by a reactive ion etching (RIE) method withoutusing a mask pattern of a resist film to allow the silicon nitride film60 to remain on the side surface of the gate electrode, as shown FIG.26. As a result, formed is the gate side wall film 61 consisting of thesilicon nitride film 59, the silicon oxide film 58 and the siliconnitride 60. Further, an n⁺-type diffusion layer 63 and a p⁺-typediffusion layer (not shown) forming the source and drain regions areselectively formed by ion implantation using a mask prepared by alithography method in the nMOS transistor and the pMOS transistor,respectively.

Preparation of the gate electrode portion characterizing the thirdembodiment of the present invention is finished by the steps describedabove. Then, the ordinary manufacturing process of MOS-FET is followedfor manufacturing a desired semiconductor device.

For example, the subsequent manufacturing process in the thirdembodiment of the present invention is as follows. In the first step, aresist pattern is selectively formed on the gate electrode alone as inthe second embodiment, followed by etching the silicon oxide film 58 andthe gate insulating film 52 positioned in the vicinity of the gateelectrode and subsequently removing the resist pattern. Then, a titaniumfilm is deposited in a thickness of 20 nm, followed by depositing atitanium nitride film in a thickness of 70 nm on the titanium film.Further, a lamp annealing is applied to the stacked structure consistingof the titanium film and the titanium nitride film at 650° C. for 30seconds under a nitrogen gas atmosphere so as to carry out reactionbetween the silicon semiconductor substrate 50 and titanium to form atitanium silicide film. Then, the unreacted titanium and titaniumnitride are selectively removed by using a mixed solution consisting ofsulfuric acid and hydrogen peroxide solution. Further, a phase change isbrought about in the titanium silicide film by a lamp annealing at 800°C. for 30 seconds so as to form a C54 phase of a low resistivity.

After formation of the C54 phase, an interlayer insulating film such asa BPSG film is deposited in a thickness of 700 nm, followed by forming acontact hole in the interlayer insulating film. Further, a conductivefilm is deposited on the resultant structure, followed by patterning theconductive film to form a wiring layer.

In the third embodiment, the tungsten layer 54 included in the gateelectrode is covered with the silicon oxide films 56, 58 acting as a capfilm and with the silicon oxide film 58 forming a gate side wall film.Therefore, even if defects such as pin holes are present in the siliconnitride films 55, 57 and 60 forming the cap film and the gate side wallfilm, a mixed solution of sulfuric acid and hydrogen peroxide solutiondoes not intrude into the gate electrode in the step of selectivelyremoving the unreacted titanium and titanium nitride. Naturally, thetungsten layer 54 included in the gate electrode is prevented from beingdissolved in the mixed solution.

It should also be noted that the side surface of the tungsten layer 54is covered with the silicon oxide film 58. Also, the upper surface ofthe tungsten layer 54 is covered with the silicon oxide films 56, 58.Thus, when the silicon nitride film 60 forming a gate side wall film isdeposited on the side surface of the gate electrode, the oxidizing agentwithin the atmosphere is prevented from intruding into the gateelectrode through the defects such as pin holes of the silicon nitridefilm 55 and the silicon nitride film 57 used as a cap film. Naturally,the tungsten layer 54 included in the gate electrode is prevented frombeing oxidized by the oxidizing agent within the atmosphere.

What should also be noted is that, in the step of forming a contact holeby self-alignment, the silicon nitride film 57 acting as a gateprotective film (cap film) is formed on the gate electrode. Since thesilicon nitride film 57 acts as an etching stopper on the gateelectrode, the gate electrode is not corroded.

The silicon nitride film 55 can be formed by a single depositingoperation. Alternatively, it is possible to repeat several times thesilicon nitride deposition and interruption of the deposition such thatthe nitride film 55 is formed by several times of the silicon nitridedeposition. In this case, even if pin holes are formed in the siliconnitride layer deposited in the previous depositing operation, these pinholes are closed by the silicon nitride layer deposited in thesubsequent depositing operation. It follows that it is possible toprevent the pin holes from extending throughout the silicon nitride film55 in its thickness direction. It is also possible to form each of thesilicon nitride films 57, 59 and 60 by several times of the siliconnitride deposition. In this case, the mixed solution consisting ofsulfuric acid and a hydrogen peroxide solution is prevented frompermeating through the silicon nitride films 55, 57, 59 or 60 to reachthe gate electrode.

As described above, according to the third embodiment of the presentinvention, the mixed solution of sulfuric acid and hydrogen peroxidesolution used in forming the silicide layer in the source and drainregions (salicide technology) is prevented from intruding into the gateelectrode through the defects such as pin holes of the silicon nitridefilm used as a gate protective film (cap film and gate side wall film).As a result, it is possible to prevent the tungsten layer included inthe gate electrode from being dissolved in the mixed solution.Similarly, in the resist removing step for removing the resist used inthe patterning step, the removing solution for removing the resist isprevented from intruding into the gate electrode through the defectssuch as pin holes of the silicon nitride film used as a gate protectivefilm (cap film and gate side wall film). It follows that the tungstenlayer included in the gate electrode is prevented from being dissolvedin the removing solution.

Also, the upper surface of the tungsten layer included in the gateelectrode is covered with a silicon oxide film. Therefore, when asilicon nitride film used as a gate side wall film is deposited on thetungsten layer, the oxidizing agent within the atmosphere is preventedfrom intruding into the gate electrode through the defects such as pinholes of the silicon nitride film used as a cap film. Naturally, thetungsten layer included in the gate electrode is prevented from beingoxidized.

Further, in the third embodiment of the present invention, since then⁺-type diffusion layer forming an active region is covered with asilicon oxide film, the active region is prevented from being exposeddirectly to a plasma in the step of forming a gate side wall by applyinga reactive ion etching to the silicon nitride film. As a result, it ispossible to prevent impurities derived from the reactive ion etchingfrom entering the active region. It is also possible to suppress damagedone to the active region.

In the third embodiment described above, the gate electrode is of astacked structure consisting of a polysilicon layer and a tungstenlayer. However, it is also possible for the stacked structure to consistof a polysilicon layer and another metal layer.

As described above, the present invention provides a semiconductordevice in which a gate electrode of a stacked structure consisting of apolysilicon layer and a metal layer is not damaged or deteriorated, anda method of manufacturing the same.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1-6. (canceled)
 7. A semiconductor device comprising: a gate electrodehaving a stacked structure of a polysilicon layer and a metal layer; acap insulating film formed on an upper surface of the gate electrode,wherein said cap insulating film including a first silicon oxide filmformed on the upper surface of the gate electrode, a first siliconnitride film formed on the first silicon oxide film, and a secondsilicon oxide film formed on the first silicon nitride film; and a sidewall insulating film formed on a side wall of the gate electrode, saidside wall insulating film including a silicon oxide film and a siliconnitride film of at least two layers.